As the geometry size of the silicon-based metal-oxide-semiconductor field effect transistor (MOSFET) shrinks to a nanometer level, traditional methods to improve performance and integration degree by reducing the size of the transistor is facing dual limitation tests both in physical and technical aspects. In order to further improve the performance of the transistor, one of the effective methods is to introduce a channel material of high mobility.
Germanium and Group III-V compound semiconductors are considered to be preferred materials for the next generation of high-speed CMOS circuits because of the high mobility of holes and electrons. However, the current technologies for fabricating the germanium-based and Group III-V compound-based MOS devices are not yet matured. If a high-K gate dielectric layer is deposited on a substrate directly, defects such as high interface state density and poor interface quality may be existed at the interface, affecting the performance of the germanium-based and Group III-V compound-based MOS devices.